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A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

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posted on 2024-08-21, 03:54 authored by Sandipan Pal, Bijoy Kumar Upadhyaya, Tanmoy Majumder, Narottam DasNarottam Das, Abhishek Bhattacharjee
In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

History

Volume

6

Issue

2

Start Page

1

End Page

15

Number of Pages

15

eISSN

2631-8695

Publisher

IOP Publishing

Additional Rights

CC BY 4.0

Peer Reviewed

  • Yes

Open Access

  • Yes

Acceptance Date

2024-06-13

Author Research Institute

  • Centre for Intelligent Systems

Era Eligible

  • Yes

Journal

Engineering Research Express

Article Number

025361

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